Document Type : Research Articles

Author

Department of Electrical Engineering, Shahid Sattari Aeronautical University of Science and Technology, Tehran, Iran

Abstract

This paper proposes a new mismatch cancelation technique for quadrature delta-sigma modulators (QDSM). In this approach, a high speed and simple structure dynamic element matching (DEM) based on homogenization and time-division (HTD) is designed. In addition, I and Q digital-to-analog converters (DACs) are merged into one complex DAC (C_DAC) for quadrature mismatch cancelation which leads to near-perfect I/Q balance. A third-order multi-bit continuous-time (CT) QDSM for a WCDMA LOW-IF receiver is designed and implemented in 180 nm CMOS technology to investigate the effects of the proposed DEM. The proposed DEM method and DWA algorithm are applied to the QDSM with 2% mismatch errors in DAC cells and compared two outputs PSD effects. Simulation results show that the modulator achieves a signal-to-noise ratio (SNR) of 74 dB and 74.2 dB for the proposed method and DWA, respectively, while the proposed method is simpler and faster than the data weighted averaging (DWA) algorithm.

Keywords

[1] Y. A. Bryukhanov and Y. A. Lukashevich, "Nonlinear
distortions caused by sigma‒delta analog-digital conversion
of signals," Journal of Communications Technology and Electronics, vol. 62, pp. 219-228, 2017.

[2] J. Talebzadeh and I. Kale, "A novel two-channel continuous-
time time-interleaved 3rd-order sigma-delta modulator with
integrator-sharing topology," Analog Integrated Circuits and
Signal Processing, pp. 1-11, 2018.

[3] J. Arias, P. Kiss, V. Prodanov, V. Boccuzzi, M. Banu, D.Bisbal, et al., "A 32-mW 320-MHz continuous-time complex
delta-sigma ADC for multi-mode wireless-LAN receivers,"
Solid-State Circuits, IEEE Journal of, vol. 41, pp. 339-351,
2006.

[4] C.-Y. Ho, W.-S. Chan, Y.-Y. Lin, and T.-H. Lin, "A quadrature
bandpass continuous-time delta-sigma modulator for a tri-
mode GSM-EDGE/UMTS/DVB-T receiver," Solid-State
Circuits, IEEE Journal of, vol. 46, pp. 2571-2582, 2011.

[5] A. Celin and A. Gerosa, "Optimal DWA design in scaled
CMOS technologies for mismatch cancellation in multibit ΣΔ
ADCs," in Circuits and Systems (ISCAS), 2015 IEEE
International Symposium on, 2015, pp. 1454-1457.

[6] S. Kundu and J. Paramesh, "DAC mismatch shaping for
quadrature sigma-delta data converters," in IEEE Midwest
Symposium on Circuits and Systems, 2015.

[7] S. Javahernia, E. N. Aghdam, and P. Torkzadeh, "A CT ΔΣ
modulator using 4-bit asynchronous SAR quantizer and
MPDWA DEM," AEU-International Journal of Electronics
and Communications, vol. 99, pp. 236-246, 2019.

[8] R. López-Holloway and M. García, "A lowcomplexity data
weighterd averaging (DWA) algorithm implementation," in
The XIII Workshop IBERCHIP IWS Workshop, Lima, Peru,
2007.

[9] D.-H. Lee, C.-C. Li, and T.-H. Kuo, "High-speed low-
complexity implementation for data weighted averaging
algorithm [/spl Sigma//spl Delta/modulator applications]," in
ASIC, 2002. Proceedings. 2002 IEEE Asia-Pacific
Conference on, 2002, pp. 283-286.

[10] E. Aghdam and P. Benabes, "Higher order dynamic element
matching by shortened tree-structure in delta-sigma
modulators," in Circuit Theory and Design, 2005. Proceedings
of the 2005 European Conference on, 2005, pp. I/201-I/204
vol. 1.

[11] S. Pavan, R. Schreier, and G. C. Temes, Understanding Delta-
Sigma Data Converters: John Wiley & Sons, 2017.

[12] J. Hu, J. Hegt, A. van Roermund, and S. F. Ouzounov,
"Higher-order DWA in bandpass delta-sigma modulators and
its implementation," in Circuits and Systems (ISCAS), 2016
IEEE International Symposium on, 2016, pp. 73-76.

[13] R. Schreier and G. C. Temes, Understanding delta-sigma data
converters vol. 74: IEEE press Piscataway, NJ, 2005.

[14] S. J. Yi, S.-H. Kim, H.-G. Jeong, and S.-I. Cho, "A 3 rd order
3bit Sigma-Delta Modulator with Reduced Delay Time of
Data Weighted Averaging," World Academy of Science,
Engineering and Technology, International Journal of
Computer, Electrical, Automation, Control and Information
Engineering, vol. 4, pp. 1688-1691, 2010.

[15] A. Celin and A. Gerosa, "A reduced hardware complexity
data-weighted averaging algorithm with no tonal behavior," in
Circuits and Systems (ISCAS), 2016 IEEE International
Symposium on, 2016, pp. 702-705.

[16] Y. Hasanpour, E. N. Aghdam, V. Sabouhi, and M. M. Sasan,
"BandPass Dynamic Element Matching for low OSR high
resolution Delta Sigma Modulators," in Electronic Devices,
Systems and Applications (ICEDSA), 2011 International
Conference on, 2011, pp. 232-236.

[17] L. J. Breems, E. C. Dijkmans, and J. H. Huijsing, "A
quadrature data-dependent DEM algorithm to improve image
rejection of a complex/spl Sigma//spl Delta/modulator," in
Solid-State Circuits Conference, 2001. Digest of Technical
Papers. ISSCC. 2001 IEEE International, 2001, pp. 48-49.

[18] B. Li and K.-P. Pun, "A High Image-Rejection SC
Quadrature Bandpass DSM for Low-IF Receivers," Circuits
and Systems I: Regular Papers, IEEE Transactions on, vol. 61, pp. 92-105, 2014.
[19] D. Li, Y.-T. Yang, Z.-C. Shi, and Y. Liu, "A low-distortion
multi-bit sigma–delta ADC with mismatch-shaping DACs for
WLAN applications," Microelectronics Journal, vol. 46, pp.
52-58, 2015.

[20] F. Gerfers and M. Ortmanns, Continuous-time sigma-delta
A/D conversion: fundamentals, performance limits and robust
implementations vol. 21: Springer Science & Business Media,
2006.

[21] M. Tamaddon and M. Yavari, "High-performance time-based
continuous-time sigma-delta modulators using single-opamp
resonator and noise-shaped quantizer," Microelectronics
Journal, vol. 56, pp. 110-121, 2016.

[22] A. Shamsi and E. Najafi Aghdam, "Continuous Time
Feedforward Quadrature Delta Sigma Modulator Design
Omitting the Power Hungry adders for LOW-IF Receivers,"
TABRIZ JOURNAL OF ELECTRICAL ENGINEERING,
vol. 49, pp. 295-305, 2019.

[23] J. Zhang, Y. Xu, Z. Zhang, Y. Sun, Z. Wang, and B. Chi, "A
10-b Fourth-Order Quadrature Bandpass Continuous-Time
$SigmaDelta $ Modulator With 33-MHz Bandwidth for a
Dual-Channel GNSS Receiver," IEEE Transactions on
Microwave Theory and Techniques, vol. 65, pp. 1303-1314,
2017.

[24] T. C. Carusone, D. Johns, and K. Martin, Analog Integrated
Circuit Design: Wiley, 2011.

[25] B. Razavi, Design of Analog CMOS Integrated Circuits:
McGraw-Hill Education, 2016.

[26] B. H. Seyedhosseinzadeh and M. Yavari, "AN EFFICIENT
LOW-POWER SIGMA-DELTA MODULATOR FOR
MULTI-STANDARD WIRELESS APPLICATIONS,"
Journal of Circuits, Systems, and Computers, vol. 21, p.
1250028, 2012.

[27] M. Bolatkale, L. J. Breems, and K. A. Makinwa, High speed
and wide bandwidth delta-sigma ADCs: Springer, 2014.

[28] A. Atac, L. Liao, Y. Wang, M. Schleyer, Y. Zhang, R.
Wunderlich, et al., "A 1.7 mW quadrature bandpass ΔΣ ADC
with 1MHz BW and 60dB DR at 1MHz IF," in Circuits and
Systems (ISCAS), 2013 IEEE International Symposium on,
2013, pp. 1039-1042.

[29] A. Atac, R. Wunderlich, and S. Heinen, "A variable
bandwidth & IF, continuous time ΔΣ modulator for low power
low-IF receivers," in New Circuits and Systems Conference
(NEWCAS), 2011 IEEE 9th International, 2011, pp. 362-365.

[30] T. Saalfeld, A. Atac, L. Liao, R. Wunderlich, and S. Heinen,
"A 2.3 mW quadrature bandpass continuous-time??
modulator with reconfigurable quantizer," in Ph. D. Research
in Microelectronics and Electronics (PRIME), 2016 12th
Conference on, 2016, pp. 1-4.

[31] a. shamsi, "Reconfigurable CT QDSM with mismatch
shaping dedicated to multi-mode low-IF receivers,"
International Journal of Industrial Electronics, Control and
Optimization, vol. 2, pp. 257-264, 2019.