Design a PLL for Fractional Frequency Synthesizers using DDSM with Reduced Hardware

Jahanpanah, Leila; Sadatnoori, Seyed Ali; Chaharmahali, Iman

doi:10.22111/ieco.2022.41006.1402

Document Type : Research Articles

Authors

¹ Department of electrical engineering, Mahshahr branch, Islamic Azad university, Mahshahr, Iran

² Department of electrical engineering, Shoushtar branch, Islamic Azad university, Shoushtar, Iran

³ Department of electrical engineering, Andimeshk branch, Islamic Azad university, Andimeshk, Iran

https://doi.org/10.22111/ieco.2022.41006.1402

Abstract

Phase locked loop (PLL) circuits are widely used in fractional frequency synthesizers. In these synthesizers, fractional multiples of the reference frequency can be synthesized, so the reference frequency and the bandwidth of the loop can be increased. This frequency synthesizer is commonly used due to its flexibility and convenient frequency adjustment. In this paper, a PLL circuit of the transistor level is designed in which a hybrid digital sigma-delta modulator with reduced hardware is used. This Digital Delta-Sigma Modulator (DDSM) has four stages that have a lower noise level and power consumption than the conventional type. This PLL circuit has a third-order loop filter and a voltage-controlled oscillator of the NMOS type. In the PLL circuit, two counters are used in its feedback path. In the proposed divider, there is a dual divider P / P + 1 (in this case 5, 6) which divides its input signal by 5, 6 according to the control input. A design example for the PLL is provided. A third stage digital Delta-Sigma modulator with reduced hardware is also used to control these counters. This modulator has less power consumption than the conventional method and has less number of transistors by 85%.

Keywords

20.1001.1.26453517.2022.5.2.6.1

Main Subjects

Electronics

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Design a PLL for Fractional Frequency Synthesizers using DDSM with Reduced Hardware

References

References

Volume 5, Issue 2June 2022Pages 177-187

Volume 5, Issue 2
June 2022
Pages 177-187