Document Type : Research Articles


Department of Electrical Engineering, Shahid Sattari Aeronautical University of Science and Technology, Tehran, Iran


A reconfigurable third-order multi-bit continuous-time quadrature delta-sigma modulator (CT-QDSM) with mismatch error correction is reported in this paper. This modulator is designed for a tri-mode WLAN/WCDMA/GSM Low-IF (Intermediate Frequency) receiver. A three-bit quantizer is utilized to achieve the bandwidth (BW) and signal to noise ratio (SNR) required in WLAN/WCDMA standards. In this modulator, the adders are eliminated to optimize the power consumption. The excess loop delay of modulator compensated by half of the sampling period of quantizer. The reconfigurable dynamic element matching (DEM) is proposed to eliminate the mismatch error. Therefore, the I and Q mismatch error are alleviated by designing the data weighted average (DWA) and homogeneous block (HB) circuits for WCDMA/WLAN modes respectively. In addition, the complex_digital to analog converter (C_DAC) is designed to eliminate the mismatch between I and Q paths. Implemented in 180 nm CMOS, achieves 53.6/74.2/81.63 dB SNR and figure-of-merits (FoM) of 0.863/0.495/1.63 pJ/ (conversion step) with a 20/2/0.2 MHz BW for WLAN/WCDMA/GSM operational mode.


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