Electronics
Hosein Malekpoor; mehdi hamidkhani
Abstract
A compact microstrip antenna by applying a parasitic artificial magnetic conductor (AMC), is proposed for facilitating 4G and 5G wireless communications. The antenna design includes microstrip dipoles fed by a T-shaped feedline. Notably, the antenna achieves a measured bandwidth of 5.32-6.73 GHz (with ...
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A compact microstrip antenna by applying a parasitic artificial magnetic conductor (AMC), is proposed for facilitating 4G and 5G wireless communications. The antenna design includes microstrip dipoles fed by a T-shaped feedline. Notably, the antenna achieves a measured bandwidth of 5.32-6.73 GHz (with S11≤ -10 dB). To enhance performance, a proposed parasitic AMC reflector is integrated into the antenna structure. Incorporating an 8×8 AMC array, the antenna extends its -10 dB measured bandwidth from 4.55 to 6.83 GHz, catering to both 4G and 5G communication standards. Comparative analysis with an antenna lacking AMC reveals a reduced size of 34%, alongside a notable gain of 8 dBi and uni-directional radiation patterns. The efficiency and gain of all elements are approximately 90% and 8 dBi, respectively. Moreover, the introduction of an AMC unit cell, well-founded on a parasitic patch, resonates at 6.12 GHz with a bandwidth extending from 5.25 to 7.15 GHz. Furthermore, the offered equivalent transmission line model of the antenna with the AMC is demonstrated, yielding desirable results. This model accurately predicts the input impedance of the antenna with AMC across a broad frequency band ranging from 4.61 to 6.72 GHz. This comprehensive study demonstrates the effectiveness and versatility of the offered model in characterizing the operating band's behavior of the antenna across a wide frequency band to facilitate its design and optimization for various applications.
Electronics
Bahram Rashidi
Abstract
This paper presents the design and hardware implementation of an efficient and optimal induction heating circuit for induction sealing. The circuit has a low implementation cost, so the proposed system with a simple and efficient structure can cover the needs of this technology field. Here, the focus ...
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This paper presents the design and hardware implementation of an efficient and optimal induction heating circuit for induction sealing. The circuit has a low implementation cost, so the proposed system with a simple and efficient structure can cover the needs of this technology field. Here, the focus is on the implementation process and practical tips in this field. The proposed induction sealing circuit uses zero-voltage switching technology with parallel MOSFETs. In this structure, by using inductors and capacitors with appropriate tolerable current and voltage, it can provide the power and frequency of the output signal applied to the induction coil for various applications. The use of transistors with suitable current capability makes the circuit appropriate for applications that require stronger magnetic fields. In addition, the induction coil has an elliptical structure, which makes it efficient for sealing a wide range of bottles. It is constructed using Litz wire to reduce power loss in the coil. In the presented structure, the frequency of the output signal is equal to 31 kHz, which is suitable for creating an eddy current in the aluminum foil in the bottle caps. The circuit has been tested and investigated and has acceptable sealing for various industries.
Electronics
Farid Khamouei Touli; Javad Yavand Hasani
Abstract
Radiofrequency microelectromechanical system (RF-MEMS) switches are utilized across a broad spectrum of industries, telecommunications, aerospace and smartphone technology.Herein, we proposed a new numerical and simulation analysis approach for spring constant (k) values as the characteristic mechanical ...
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Radiofrequency microelectromechanical system (RF-MEMS) switches are utilized across a broad spectrum of industries, telecommunications, aerospace and smartphone technology.Herein, we proposed a new numerical and simulation analysis approach for spring constant (k) values as the characteristic mechanical parameters of RF MEMSs using the modified energy method (MEM). The proposed RF-MEMS switch was analyzed and simulated using the COMSOL package, and the findings confirmed that the alteration in the position and length (L) of the beams not only diminishes k significantly but also provides actuation-voltage VAC ultrasensitive structures and great concomitance between numerical and simulation k and VAC values. VAC value for the L-dependent numerical k (0.07 N m-1) was calculated to be 1.61 V which was validated with simulation outputs at 0.08 N m-1 and 1.80 V for k and VAC, respectively. Additionally, the switching time (ts), Von Mises Stress (VMS), natural frequency (fn) and mass (m) characteristic mechanical parameters were found to be 25.60 µs, 4.50 MPa, 3118.60 Hz , and0.21 ng, respectively. RF analysis was conducted in HFSS, revealing promising simulation results for the studied RF-MEMS switches. The return loss demonstrates excellent performance, registering better than -1 dB at 46 GHz. Furthermore, the insertion loss is noteworthy, exceeding expectations with values better than -0.7 dB at 46 GHz. Importantly, the isolation is impressive, exceeding -25 dB across the frequency range from 40 GHz to 35 GHz, all achieved with a modest actuation voltage of 1.8 V. This study contributes valuable insights intothe design and application of low-actuation-voltage RF-MEMS switches.
Electronics
Farzaneh Yousefzadeh Ahari; Mousa Yousefi; Khalil Monfaredi
Abstract
The essential reason for implementing multilevel processing systems is to reduce the number of semiconductor elements and hence the complexity of system. Multilevel processing systems are realized much easier by carbon nanotube field effect transistors (CNTFET) than MOSFET transistors due to the CNTFET ...
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The essential reason for implementing multilevel processing systems is to reduce the number of semiconductor elements and hence the complexity of system. Multilevel processing systems are realized much easier by carbon nanotube field effect transistors (CNTFET) than MOSFET transistors due to the CNTFET transistors' adjustable threshold voltage capabilities. In this paper, an efficient quaternary full-adder based on CNTFET technology is presented which consists of two half adder blocks, a quaternary decoder and a carry generator circuit. In the proposed architecture, the base-two and base-four circuit design techniques are combined to take the full advantages of both techniques namely simple implementation and low chip area occupation of the entire proposed quaternary full-adder. The proposed structure is evaluated using the Stanford 32nm CNTFET library in HSPICE software. The simulation results for the proposed full-adder structure utilizing a supply voltage of 0.9 volts, reveals the power consumption, propagation delay and energy index equal to 2.67 μW, 40 ps, and 10.68 aJ, respectively.
Electronics
Hamid Kazemi Karyani; Esmaeil Najafiaghdam
Abstract
This article presents development and implementation of an integer N-type Phase Locked Loop (PLL) module with two output frequencies of 1 and 4 GHz, each having a phase noise better than -110dBC/Hz@10k. The structure has 0 and 10dBm power levels at 1 and 4GHz output frequencies, respectively. Having ...
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This article presents development and implementation of an integer N-type Phase Locked Loop (PLL) module with two output frequencies of 1 and 4 GHz, each having a phase noise better than -110dBC/Hz@10k. The structure has 0 and 10dBm power levels at 1 and 4GHz output frequencies, respectively. Having two different outputs of 1 and 4 GHz at once, in addition to the 1.1 and 4.4GHz realized by the capability included in this design in which two additional outputs can be achieved by using the pins A0 to A4 and altering their status, makes this structure a good candidate for mass production. A two-step frequency division is employed in this work. The first step is realized using the frequency divider of order 4, and the second step is implemented inside the HMC440 IC, including a PFD and a counter. Compared to typical methods, this method presents a clean output by suppressing the spurs meant to be manifested using a single-step frequency division. This PLL is constructed in discrete and modular modes and employed in transceivers’ up-converter and down-converter blocks, Satellite communications, Cable TV links (CATV), Local Area Networks (LAN), Global Positioning Systems (GPS), test equipment, digital radios, military and commercial communications. For a specific example, the 4GHz frequency is used to up-converte or down-converte the received signals, and the 1-GHz frequency is usually used for the synthesizer module clock frequency. Advanced Design System (ADS) was used in the design, and OrCAD was used in the schematic design of the PLL module.
Electronics
Bahram Rashidi
Abstract
In this paper, we design a lightweight and modified random key generation for PRESENT block cipher which is applicable in the encryption of the digital signals. In the block ciphers, the master key is used directly in the encryption process for the data (plaintext). But in this work, a master key (initial ...
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In this paper, we design a lightweight and modified random key generation for PRESENT block cipher which is applicable in the encryption of the digital signals. In the block ciphers, the master key is used directly in the encryption process for the data (plaintext). But in this work, a master key (initial key) is used to derive the new random master keys (random session keys) and use these keys for the encryption process. The use of random keys will overcome the brute force attack that can be applied to the PRESENT cipher. The random session keys generated will produce different ciphertexts for the same plaintext for every session. In this approach, we take advantage of the block cipher to produce random keys. The PRESENT cipher is shared in both random key generation and encryption process. Therefore, the proposed structure has both random key generation and data encryption in a unified circuit. This property reduces hardware resources. The implementation results, in 180 nm CMOS technologies, show the proposed structure is comparable in terms of area and delay with other works.
Electronics
Habibollah Zolfkhani; Alireza Sharifi
Abstract
In this paper, a method is presented to design and implement ultra-wideband phase shifters, in frequency ranges higher than 10 GHz, with fractional bandwidth near a hundred percent. The phase shifter is constructed from microstrip transmission lines and short circuit stubs. In comparison with conventional ...
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In this paper, a method is presented to design and implement ultra-wideband phase shifters, in frequency ranges higher than 10 GHz, with fractional bandwidth near a hundred percent. The phase shifter is constructed from microstrip transmission lines and short circuit stubs. In comparison with conventional phase shifters which are composed of microstrip coupled lines and multilayer structures, the proposed phase shifter has advantages from the implementation and fabrication viewpoint. The design and optimization method is in such a way that arbitrary phase shift, source and load impedances may be considered in the design. To optimize the circuit dimension, a computer code is written, and two design examples are considered. The computer code is based on closed form equations for microstrip transmission lines and available circuit models for it and utilizes microwave network equations. Its results are then improved with electromagnetic full-wave packages to consider the parasitic effects of microstrip T-junctions. Two design cases are included, in the first design, the case of a 45 degrees phase shifter with a standard 50 ohms source and load impedances is investigated. In the second design case, the case of a 90 degrees phase shifter with 50 ohms input impedances and 75 ohm non-standard output impedances is considered. By observing the full-wave simulation results as well as the fabrication and measurement results in these examples, it is clear that the design goals are highly satisfied by this method.
Electronics
Leila Jahanpanah; Seyed Ali Sadatnoori; Iman Chaharmahali
Abstract
Phase locked loop (PLL) circuits are widely used in fractional frequency synthesizers. In these synthesizers, fractional multiples of the reference frequency can be synthesized, so the reference frequency and the bandwidth of the loop can be increased. This frequency synthesizer is commonly used due ...
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Phase locked loop (PLL) circuits are widely used in fractional frequency synthesizers. In these synthesizers, fractional multiples of the reference frequency can be synthesized, so the reference frequency and the bandwidth of the loop can be increased. This frequency synthesizer is commonly used due to its flexibility and convenient frequency adjustment. In this paper, a PLL circuit of the transistor level is designed in which a hybrid digital sigma-delta modulator with reduced hardware is used. This Digital Delta-Sigma Modulator (DDSM) has four stages that have a lower noise level and power consumption than the conventional type. This PLL circuit has a third-order loop filter and a voltage-controlled oscillator of the NMOS type. In the PLL circuit, two counters are used in its feedback path. In the proposed divider, there is a dual divider P / P + 1 (in this case 5, 6) which divides its input signal by 5, 6 according to the control input. A design example for the PLL is provided. A third stage digital Delta-Sigma modulator with reduced hardware is also used to control these counters. This modulator has less power consumption than the conventional method and has less number of transistors by 85%.
Electronics
alireza shamsi
Abstract
This paper proposes a new mismatch cancelation technique for quadrature delta-sigma modulators (QDSM). In this approach, a high speed and simple structure dynamic element matching (DEM) based on homogenization and time-division (HTD) is designed. In addition, I and Q digital-to-analog converters (DACs) ...
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This paper proposes a new mismatch cancelation technique for quadrature delta-sigma modulators (QDSM). In this approach, a high speed and simple structure dynamic element matching (DEM) based on homogenization and time-division (HTD) is designed. In addition, I and Q digital-to-analog converters (DACs) are merged into one complex DAC (C_DAC) for quadrature mismatch cancelation which leads to near-perfect I/Q balance. A third-order multi-bit continuous-time (CT) QDSM for a WCDMA LOW-IF receiver is designed and implemented in 180 nm CMOS technology to investigate the effects of the proposed DEM. The proposed DEM method and DWA algorithm are applied to the QDSM with 2% mismatch errors in DAC cells and compared two outputs PSD effects. Simulation results show that the modulator achieves a signal-to-noise ratio (SNR) of 74 dB and 74.2 dB for the proposed method and DWA, respectively, while the proposed method is simpler and faster than the data weighted averaging (DWA) algorithm.
Electronics
Hamideh Dashti
Abstract
In this paper, for the first time, effects of external electromagnetic fields on a coplanar waveguide (CPW) are numerically studied by means of the method of finite elements. Two CPW lines with different geometry and dielectric substrate permittivity are considered. Both lines have characteristic impedance ...
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In this paper, for the first time, effects of external electromagnetic fields on a coplanar waveguide (CPW) are numerically studied by means of the method of finite elements. Two CPW lines with different geometry and dielectric substrate permittivity are considered. Both lines have characteristic impedance of 50 Ω. Induced electric and magnetic fields on the two CPW lines are analyzed by illuminating the structure with a plane wave. The uniform plane wave with fixed frequency at 3 GHz is considered as the incident field. The influences of the incidence angle and dielectric substrate permittivity are investigated. For this purpose, two incidence planes are considered and, for each case, two polarizations, parallel and perpendicular, for incidence electric field relative to incidence planes are studied. According to the results, for the two CPW lines terminated with their characteristic impedance at both ends and the incident plane wave with electric-field intensity of 1 V/m at f = 3 GHz with incidence angles of 22.5Ëš and 45Ëš, maximum peaks of the induced field occur and also, depending on the incidence plane, incidence angle and E-field polarization, even or odd quasi-TEM mode of the CPW line can be propagated.
Electronics
alireza shamsi
Abstract
A reconfigurable third-order multi-bit continuous-time quadrature delta-sigma modulator (CT-QDSM) with mismatch error correction is reported in this paper. This modulator is designed for a tri-mode WLAN/WCDMA/GSM Low-IF (Intermediate Frequency) receiver. A three-bit quantizer is utilized to achieve the ...
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A reconfigurable third-order multi-bit continuous-time quadrature delta-sigma modulator (CT-QDSM) with mismatch error correction is reported in this paper. This modulator is designed for a tri-mode WLAN/WCDMA/GSM Low-IF (Intermediate Frequency) receiver. A three-bit quantizer is utilized to achieve the bandwidth (BW) and signal to noise ratio (SNR) required in WLAN/WCDMA standards. In this modulator, the adders are eliminated to optimize the power consumption. The excess loop delay of modulator compensated by half of the sampling period of quantizer. The reconfigurable dynamic element matching (DEM) is proposed to eliminate the mismatch error. Therefore, the I and Q mismatch error are alleviated by designing the data weighted average (DWA) and homogeneous block (HB) circuits for WCDMA/WLAN modes respectively. In addition, the complex_digital to analog converter (C_DAC) is designed to eliminate the mismatch between I and Q paths. Implemented in 180 nm CMOS, achieves 53.6/74.2/81.63 dB SNR and figure-of-merits (FoM) of 0.863/0.495/1.63 pJ/ (conversion step) with a 20/2/0.2 MHz BW for WLAN/WCDMA/GSM operational mode.