Electronics
Khalil Monfaredi; Mousa Yousefi
Abstract
Objective: In this paper, a trans-conductance amplifier based on Common Mode Rejection Ratio (CMRR) enhancement block is presented. The proposed block is capable of eliminating common mode signals at input stage. This feature improves the gain and CMRR of the amplifier substantially. The Cascode structure ...
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Objective: In this paper, a trans-conductance amplifier based on Common Mode Rejection Ratio (CMRR) enhancement block is presented. The proposed block is capable of eliminating common mode signals at input stage. This feature improves the gain and CMRR of the amplifier substantially. The Cascode structure is also eliminated in proposed architecture, which resulted in favorably reduced power consumption due to low supply voltage requirements. Materials and Methods: The presented OTA is simulated in 180nm CMOS technology at Cadence Spectre environment with 1.5 v supply voltage proving it appropriate for low-voltage applications. The bias current of the proposed circuit is very low value of 3.9 μA. Results: Gain and phase margin for this block are achieved to be 83.96 dB and 61.68 degree, respectively. These results achieved while the circuit drive a 5pF load at its output. The power consumption of the proposed amplifier is interestingly very low value of 5.9 μW. Conclusion: It is interestingly concluded that the achieved specifications makes the block very much suitable for low-power applications.
Electronics
Farzaneh Yousefzadeh Ahari; Mousa Yousefi; Khalil Monfaredi
Abstract
The essential reason for implementing multilevel processing systems is to reduce the number of semiconductor elements and hence the complexity of system. Multilevel processing systems are realized much easier by carbon nanotube field effect transistors (CNTFET) than MOSFET transistors due to the CNTFET ...
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The essential reason for implementing multilevel processing systems is to reduce the number of semiconductor elements and hence the complexity of system. Multilevel processing systems are realized much easier by carbon nanotube field effect transistors (CNTFET) than MOSFET transistors due to the CNTFET transistors' adjustable threshold voltage capabilities. In this paper, an efficient quaternary full-adder based on CNTFET technology is presented which consists of two half adder blocks, a quaternary decoder and a carry generator circuit. In the proposed architecture, the base-two and base-four circuit design techniques are combined to take the full advantages of both techniques namely simple implementation and low chip area occupation of the entire proposed quaternary full-adder. The proposed structure is evaluated using the Stanford 32nm CNTFET library in HSPICE software. The simulation results for the proposed full-adder structure utilizing a supply voltage of 0.9 volts, reveals the power consumption, propagation delay and energy index equal to 2.67 μW, 40 ps, and 10.68 aJ, respectively.
