Electronics
Design and Implementation of an N-type Integer Phase-locked Loop with Low Phase Noise and Two Output Frequencies at 1 and 4 GHz

Hamid Kazemi Karyani; Esmaeil Najafiaghdam

Volume 7, Issue 1 , March 2024, , Pages 29-39

https://doi.org/10.22111/ieco.2024.46858.1505

Abstract
  This article presents development and implementation of an integer N-type Phase Locked Loop (PLL) module with two output frequencies of 1 and 4 GHz, each having a phase noise better than -110dBC/Hz@10k. The structure has 0 and 10dBm power levels at 1 and 4GHz output frequencies, respectively. Having ...  Read More